The Opportunity / What we're looking for:

We believe in the power of people. We are a network strategy and technology company that is motivated by making a difference in people's lives - their productivity, their creativity, their health and comfort. That's why our engineers design and implement technologies that allow people to do great things.

We're looking for highly motivated and talented engineers who are passionate about engineering velocity and automation. You will build solutions that provide Ciena engineers robust data pathways that allow for cross-regional communication and the infrastructure to support these pathways. You will own and drive entire solutions which include service scalability, reliability, and troubleshooting

Sr. FPGA Verification Engineer:

As a Senior FPGA Verification Engineer at the Packet Access organization of Ciena, you will take on a role of technical leadership and demonstrate your deep expertise in all aspects of FPGA verification. You should have hands-on experience with verifying FPGAs for real-world products, as well as a proven ability to make effective decisions on methodology, and technique as they apply to FPGA verification and validation. You will be an important member of the FPGA Engineering team and our overall R&D engineering organization, collaborating on a daily basis with a highly skilled group of FPGA designers as well as Diag and SW engineers. This role involves project ownership and provides an excellent opportunity to showcase your verification skills and make a visible impact within the company. We are expanding the team to deliver new products into new market spaces. Take advantage of this opportunity to carve out a significant role in this rapidly growing industry!

Responsibilities:

• Develop design verification testbenches from scratch using UVM and maintain them
• Develop test plans and write directed/constrained-random verification tests
• Work with design engineers to identify design corner cases and write appropriate cover points
• Collaborate with design team to debug test cases and deliver functionally correct designs
• Close coverage measures (line, toggle, conditional as well as functional) to identify verification holes
• Work with HW, diagnostics and SW engineers to create programming sequences for lab characterization
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Write SVA (System Verilog Assertions) as part of the verification flow
• Contribute towards FPGA Verification at block and system levels, lab bringup and validation
• Lead multiple projects and mentor junior engineers
• Hands-on self-starter who can execute the steps required to fully verify a complex digital design

Qualifications:

• BS/MS in Electrical or Computer Engineering
• 10+ years of relevant experience in design verification of Networking/Packet-processing FPGAs
• 5+ years of experience developing verification collateral using System Verilog, C++ and UVM (experience creating drivers, monitors, predictor and scoreboards)
• Strong Object Oriented programming knowledge
• Expertise in developing test plans, constrained random verification, defining/implementing coverage models, and analyzing results
• Ability to write scripts (bash/csh, Python, Perl, TCL, etc.) and test automations
• Exposure with industry standard verification tools: simulators (Questa, VCS, Xcelium), code coverage tools, debug tools (Verdi, Visualizer), bug tracking tools, version control etc.
• Familiarity with testing complex designs, code and functional coverage, and SV assertions
• Work experience creating a self-checking simulation testbench from scratch.

Preferred Qualification:

• Experience with packet based protocols such as PCIe, Ethernet, SPI4, Avalon-ST, Interlaken, RoE as well as Avalon-MM, AXI, TCAM, CPRI, and I2C
• Good technical writing skills to write verification environment documents

• Any RTL design, chip bring-up, post-silicon validation experience
• Experience with formal verification methodologies

*LI-CN

Rewarding experience. Meaningful outcomes.

Making a difference in people's lives through design and implementation of leading network technologies. That's what motivates us.

A distinct way to work

Free thinking, free discussion, and collaboration are the norm. Expect more satisfying outcomes - both personal and professional.

Ciena values the diversity of our workforce and respects its employees as individuals, regardless of race, nationality, religion, sexual orientation, gender or age.

Ciena is also committed to developing inclusive, barrier-free selection processes and work environments. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific needs / accommodation measures which must be taken to enable you to be assessed in a fair and equitable manner. Information received relating to any specific needs / accommodation measures will be addressed confidentially.

What you can expect from us

• You will receive notification of your successful application
• Successful applicants will be contacted by Talent Acquisition for an initial discussion
• If suitable you will be considered for the short list and our formal interview process